• DocumentCode
    1098994
  • Title

    An optimized and reliable LDD structure for 1-µm NMOSFET based on substrate current analysis

  • Author

    Matsumoto, Yasuo ; Higuchi, Takayoshi ; Mizuno, Tomohisa ; Sawada, Shizuo ; Shinozaki, Satoshi ; Ozawa, Osamu

  • Author_Institution
    Toshiba Corporation, Kawasaki, Japan
  • Volume
    32
  • Issue
    2
  • fYear
    1985
  • fDate
    2/1/1985 12:00:00 AM
  • Firstpage
    429
  • Lastpage
    433
  • Abstract
    Optimization of the n-region concentration for n-channel MOSFET´s with a lightly doped drain (LDD) structure was investigated, based on an analysis of the substrate current characteristics. When a substrate current tailing is observed, which is peculiar to the LDDFET with a low-concentration n-region, a gate current is not observed, which suggests strong resistance against hot-carrier injection. This was confirmed by a bias stress test. The optimized surface concentration for the n-region ranges from 1 × 1018cm-3to 2.5 × 1018cm-3under negligible VTHshift and less than 25-percent driving capability degradation, compared to values for a conventional MOSFET.
  • Keywords
    Acceleration; Breakdown voltage; Degradation; Etching; Fabrication; Hot carrier injection; MOSFET circuits; Stress; Substrate hot electron injection; Testing;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/T-ED.1985.21959
  • Filename
    1484706
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1098994