Title :
A self-testing dynamic RAM chip
Author :
You, Younggap ; Hayes, John P.
Author_Institution :
The University of Michigan, Ann Arbor, MI
fDate :
2/1/1985 12:00:00 AM
Abstract :
A novel approach to making very large dynamic RAM chips self-testing is presented. It is based on two main concepts: on-chip generation of regular test sequences with very high fault coverage, and concurrent testing of storage-cell arrays to reduce overall testing time. The failure modes of a typical 64K RAM employing one-transistor cells are analyzed to identify their test requirements. A comprehensive test generation algorithm that can be implemented with minimal modification to a standard cell layout is derived. The self-checking peripheral circuits necessary to implement this testing algorithm are described, and the self-testing RAM is briefly evaluated.
Keywords :
Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Computer errors; DRAM chips; Electrical fault detection; Fault detection; Read-write memory; Very large scale integration;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/T-ED.1985.21971
