Deep-submicrometer channel design in silicon-on-insulator (SOI) MOSFET´s

Author

Su, L.T. ; Jacobs, J.B. ; Chung, J. ; Antoniadis, D.A.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA

Volume

15

Issue

5

fYear

1994

fDate

5/1/1994 12:00:00 AM

Firstpage

183

Lastpage

185

Abstract

Short-channel effects in deep-submicrometer SOI MOSFET´s are explored over a wide range of device parameters using two-dimensional numerical simulations. To obtain reduced short-channel effects in SOI over bulk technologies, the silicon film thickness must be considerably smaller than the bulk junction depth because of an additional charge-sharing phenomenon through the SOI buried oxide. The optimal design space, considering nominal and short-channel threshold voltage, shows ample design options for both fully and partially depleted devices, however, manufacturing considerations in the 0.1 μm regime may favor partially depleted devices.

Keywords

insulated gate field effect transistors; semiconductor device models; semiconductor-insulator boundaries; silicon; 0.1 micron; SOI MOSFETs; buried oxide; charge-sharing phenomenon; deep-submicrometer channel design; device parameters; fully depleted devices; optimal design space; partially depleted devices; short-channel effects; two-dimensional numerical simulations; Doping; Jacobian matrices; MOSFET circuits; Manufacturing; Numerical simulation; Parasitic capacitance; Semiconductor films; Silicon on insulator technology; Space technology; Threshold voltage;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.291592

Filename

291592