• DocumentCode
    1099510
  • Title

    A procedure for field implanting a CMOS isoplanar integrated circuit

  • Author

    Harper, Francis

  • Author_Institution
    Western Digital Corporation, Irvine, CA
  • Volume
    32
  • Issue
    3
  • fYear
    1985
  • fDate
    3/1/1985 12:00:00 AM
  • Firstpage
    720
  • Lastpage
    722
  • Abstract
    A procedure is given which allows the construction of a CMOS, isoplanar integrated circuit with independent and self-aligned field implants, for both PMOS and NMOS regions. A unique feature of this procedure is that only time-tested processing steps conventional to either PMOS or NMOS are used. After a detailed description of the process has been given, design-layout restrictions and physical results are discussed.
  • Keywords
    Bipolar transistors; CMOS integrated circuits; Capacitance; Current supplies; Electron devices; H infinity control; Radio access networks; Thyristors; Transient response; Voltage;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/T-ED.1985.22007
  • Filename
    1484753
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1099510