Title :
A procedure for field implanting a CMOS isoplanar integrated circuit
Author_Institution :
Western Digital Corporation, Irvine, CA
fDate :
3/1/1985 12:00:00 AM
Abstract :
A procedure is given which allows the construction of a CMOS, isoplanar integrated circuit with independent and self-aligned field implants, for both PMOS and NMOS regions. A unique feature of this procedure is that only time-tested processing steps conventional to either PMOS or NMOS are used. After a detailed description of the process has been given, design-layout restrictions and physical results are discussed.
Keywords :
Bipolar transistors; CMOS integrated circuits; Capacitance; Current supplies; Electron devices; H infinity control; Radio access networks; Thyristors; Transient response; Voltage;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/T-ED.1985.22007
