Improved Erasing Speed in Junctionless Flash Memory Device by ${\\rm HfO}_{2}/{\\rm Si}_{3}{\\rm N}_{4}$ Stacked Trapping Layer

Author

Chun-Yuan Chen ; Kuei-Shu Chang-Liao ; Kuen-Te Wu ; Tien-Ko Wang

Author_Institution

Dept. of Eng. & Syst. Sci., Nat. Tsing Hua Univ., Hsinchu, Taiwan

Volume

34

Issue

8

fYear

2013

fDate

Aug. 2013

Firstpage

993

Lastpage

995

Abstract

A junctionless (JL) polycrystalline-based flash memory device with HfO₂/Si₃N₄(HN) stacked trapping layer is studied for the first time. Effects of the HN stacked trapping layer on JL and inversion-mode (IM) flash devices are compared. JL device shows faster programming speed than the IM one because of its heavily doped n-channel. Specially, comparable erasing speed of JL device can be achieved by HN stacked trapping layer due to more effective electron detrapping. JL device with HN stacked trapping layer also shows better retention characteristics and keeps a larger window after 10⁵ programming/erasing cycles, which makes it promising for 3-D memory integration in the future.

Keywords

flash memories; hafnium compounds; silicon compounds; 3D memory integration; HfO₂-Si₃N₄; electron detrapping; erasing speed; heavily doped n-channel; inversion-mode flash devices; junctionless polycrystalline-based flash memory device; programming speed; retention characteristics; stacked trapping layer; ${rm Si}_{3}{rm N}_{4}$; Charge-trapping; flash memory ${rm HfO}_{2}$; high- $kappa$; junctionless; poly-Si;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2013.2265599

Filename

6542684

Improved Erasing Speed in Junctionless Flash Memory Device by Stacked Trapping Layer

Chun-Yuan Chen ; Kuei-Shu Chang-Liao ; Kuen-Te Wu ; Tien-Ko Wang

jour

Improved Erasing Speed in Junctionless Flash Memory Device by ${\\rm HfO}_{2}/{\\rm Si}_{3}{\\rm N}_{4}$ Stacked Trapping Layer