DocumentCode :
1099968
Title :
NMOS protection circuitry
Author :
Rountree, Robert N. ; Hutchins, Charles L.
Author_Institution :
Texas Instruments, Incorporated, Houston, Texas
Volume :
32
Issue :
5
fYear :
1985
fDate :
5/1/1985 12:00:00 AM
Firstpage :
910
Lastpage :
917
Abstract :
This paper discusses the major models that relate to breakdown phenomena and how they relate to protection-circuit design. The voltage-, current-, and temperature-dependent models are empirically extended to three dimensions. Using the resultant model, test structures were designed, processed, and evaluated. From this work, the key design and layout parameters for NMOS have been determined. With an optimized layout, electrostatic discharge protection up to 8 kV can be obtained.
Keywords :
Circuit testing; Electrostatic discharge; MOS devices; Poisson equations; Process design; Protection; Reliability engineering; Temperature dependence; Thermal conductivity; Voltage;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/T-ED.1985.22047
Filename :
1484793
Link To Document :
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