DocumentCode :
1099989
Title :
A trench-isolated submicrometer CMOS technology
Author :
Vyas, Hanuman P. ; Lutze, Robert S L ; Huang, J.S.T.
Author_Institution :
Honeywell, Inc., Plymouth, MN
Volume :
32
Issue :
5
fYear :
1985
fDate :
5/1/1985 12:00:00 AM
Firstpage :
926
Lastpage :
931
Abstract :
A trench-isolation technique is applied to submicrometer CMOS technology to increase packing density and to reduce latchup susceptibility. Device structure considerations and fabrication technology will be discussed. Experimental results of device characteristics using LDD-type NMOS and buried-channel-type PMOS will be presented. The technology is also suitable for fabricating bipolar devices on the same chip.
Keywords :
Annealing; CMOS technology; Doping; Electrons; Etching; Implants; Lithography; MOS devices; MOSFETs; Threshold voltage;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/T-ED.1985.22049
Filename :
1484795
Link To Document :
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