An analysis of the thermal response of power chip packages

Since power densities in integrated circuits and power semiconductor devices are continuously increasing due to miniaturization of circuitry, the design of optimum heat spreaders and heat sinks for these applications requires rather sophisticated calculational methods. The chips and spreaders are usually rectangular in shape and although the problem is three-dimensional in nature, it is usually approximated by two-dimensional configurations. Steady-state and transient analytic solutions are presented for the axisymmetric, two-dimensional, and three-dimensional spreader geometries, which can be used to calculate the thermal resistance of the base alone. To determine the thermal resistance of the chip-base combination, the one-dimensional chip thermal resistance should be added to that of the base. These analytic solutions provide calculational means which are easier than the numerical methods. The exact analytic steady-state and transient solutions developed for the axisymmetric, two-dimensional, and three-dimensional configurations are in excellent agreement with the numerical calculations. The parametric calculations provide information on the important guidelines that a packaging engineer should bear in mind while designing and optimizing heat spreaders for power semiconductor applications. These points can be summarized as follows: 1) for a given chip area there exists an optimal base area, 2) increasing the base thickness initially decreases the thermal resistance and beyond a certain limit the latter increases with base thickness, and 3) the convective heat transfer coefficient strongly affects the thermal resistance and the usual assumption of an isothermal base is not always appropriate.