A family of special purpose microprogrammable digital signal processor IC´s in an LPC vocoder system

This paper discusses a family of digital signal processor integrated circuits designed to be the fundamental building blocks of an LPC vocoder, specifically LPC analysis, AMDF pitch extraction, and LPC synthesis. The IC´s are custom designs intended to minimize silicon real estate for extremely high performance, novel DSP architectures, and high computational demand algorithms. Each IC shares a common architecture, that of a single internal data bus connecting input and output FIFO´s, multiple arithmetic logic units, registers, and a microcode control bus. Each application is microprogrammed in register transfer language providing considerable flexibility. The CMOS design of each IC allows it to implement the high performance digital signal processing algorithms with minimal power consumption. The LPC synthesis IC allows various common filter topologies and residual excitation. The AMDF IC extracts the commonly used features for pitch and voicing. The LPC analyzer IC is microprogrammed to implement a flow form PARCOR LPC analysis. Algorithm architecture tradeoffs between computational load and memory are discussed.