Title :
A 3.6 pJ/Access 480 MHz, 128 kb On-Chip SRAM With 850 MHz Boost Mode in 90 nm CMOS With Tunable Sense Amplifiers
Author :
Cosemans, Stefan ; Dehaene, Wim ; Catthoor, Francky
Author_Institution :
ESAT-MICAS Lab., Katholieke Univ. Leuven, Leuven
fDate :
7/1/2009 12:00:00 AM
Abstract :
An extremely low energy per operation, single cycle 32 bit/word, 128 kb SRAM is fabricated in 90 nm CMOS. In the 850 MHz boost mode, total energy consumption is 8.4 pJ/access. This reduces to 3.6 pJ/access in the normal 480 MHz mode and bottoms out at a very aggressive 2.7 pJ/access in the 240 MHz low power mode. Several techniques were combined to obtain these performance numbers. Short buffered local bit lines reduce the impact of the cell read current on memory delay. Extended global bitlines are used which improves delay and energy consumption and which reduces the number of sense amplifiers in the memory to 32. Cell stability and speed issues are avoided by applying selective voltage scaling. Novel, digitally tunable sense amplifiers and a tunable timing circuit cope gracefully with the stochastic variations in the periphery.
Keywords :
CMOS digital integrated circuits; SRAM chips; UHF amplifiers; low-power electronics; CMOS; cell stability; energy consumption; frequency 240 MHz; frequency 480 MHz; frequency 850 MHz; low power mode; memory delay; on-chip SRAM; selective voltage scaling; size 90 nm; storage capacity 128 Kbit; tunable sense amplifier; tunable timing circuit; Circuit stability; Delay; Dynamic voltage scaling; Energy consumption; Energy measurement; Low voltage; Random access memory; Stochastic processes; Timing; Tunable circuits and devices; SRAM; bit line hierarchy; calibrated timing; dynamic cell stability; embedded memory; low-power; selective voltage scaling; sense amplifier calibration; variability-aware design;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2009.2021925
