DocumentCode :
1100309
Title :
A receiver circuit for Josephson computer chip-to-chip logic signal transmissions
Author :
Tazoh, Yasuo ; Aoki, Katsuhiko ; Yoshikiyo, Haruo
Author_Institution :
Nippon Telegraph and Telephone Corporation, Kanagawa, Japan
Volume :
32
Issue :
6
fYear :
1985
fDate :
6/1/1985 12:00:00 AM
Firstpage :
1082
Lastpage :
1085
Abstract :
A receiver circuit for the transmission of logic signals through package connectors in a Josephson computer is developed. It utilizes new circuit construction. This construction gives operation unaffected by the noise which is induced on the signal transmission paths by high-frequency and high-level ac power current at the connectors. The power current noise reduction ratio at a power frequency of 
= 250 MHz, which corresponds to a 2-ns machine cycle, is experimentally confirmed to be 0.15.
= 250 MHz, which corresponds to a 2-ns machine cycle, is experimentally confirmed to be 0.15.Keywords :
Circuit noise; Connectors; Crosstalk; Frequency; Josephson junctions; Logic circuits; Noise level; Packaging; Protection; Superconducting device noise;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/T-ED.1985.22078
Filename :
1484824
Link To Document :
