Fabrication of fully self-aligned joint-gate CMOS structures

A six-mask process that yields stacked CMOS structures with the source and drain of both transistors self-aligned to a joint-gate electrode has been developed. The features that permit full self-alignment are an edge-defined silicon nitride "filament," used as an oxidation mask, and overlapping polysilicon "handles," used to form the top transistor source and drain regions. The individual NMOS and PMOS transistors have been characterized and together are functional in joint-gate CMOS inverters.