DocumentCode :
1100465
Title :
A single CMOS speech synthesis chip and new synthesis techniques
Author :
Inoue, Kazuo ; Wakabayashi, Kenji ; Yoshikawa, Yoshinobu ; Masuzawa, Shigeaki ; Sano, Kenji ; Kimura, Seiji
Author_Institution :
Sharp Corporation, Tenri City, Nara, Japan
Volume :
31
Issue :
1
fYear :
1983
fDate :
2/1/1983 12:00:00 AM
Firstpage :
335
Lastpage :
338
Abstract :
A single CMOS speech synthesis LSI, organized as a special purpose microcomputer containing program ROM, RAM, 32K of speech data ROM, and a D/A converter is described in this paper. The chip utilizes new speech synthesis techniques to generate high quality speech, reproducing the natural inflection and intonation of the speaker, and has been used to produce speech at a bit rate of about 3 kbits/s.
Keywords :
Circuits; Data compression; Large scale integration; Linear predictive coding; Microcomputers; Read only memory; Read-write memory; Signal processing algorithms; Signal synthesis; Speech synthesis;
fLanguage :
English
Journal_Title :
Acoustics, Speech and Signal Processing, IEEE Transactions on
Publisher :
ieee
ISSN :
0096-3518
Type :
jour
DOI :
10.1109/TASSP.1983.1164053
Filename :
1164053
Link To Document :
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