Abstract :
With a suitable adder organization it is possible to overlap the adder operation during a binary multiplication and significantly decrease the overall multiplication time. The method is explained and a prototype multiplier described. The new technique provides a very economical method of obtaining a reasonably fast multiplier.
Keywords :
Concurrent ADD cycles, parallel binary multiplier, propagating adder control signals, synchronous adder.; Adders; Circuits; Costs; Decoding; Degradation; Educational institutions; Hardware; Logic; Physics; Prototypes; Concurrent ADD cycles, parallel binary multiplier, propagating adder control signals, synchronous adder.;
