A digital adaptive filter using a memory-accumulator architecture: Theory and realization

This paper presents a novel approach to the construction of an adaptive filter making use of the so-called "distributed arithmetic" filter architecture originally suggested by Peled and Liu [7] for the realization of fixed response digital frequency filters. The technique uses only the operations of memory access, addition, and scaling, without the need for digital multiplication. Since multiplication is often quoted as the major bottleneck in digital signal processing structures, the system derives considerable advantage by the exclusion of this operation. The paper presents the derivation of a new adaptive algorithm based on this particular hardware structure, although no rigorous theoretical proof of the algorithm convergence properties is given. Computer simulations are included to demonstrate some of the basic operational characteristics of the structure. Finally, results from a hardware prototype, constructed using standard TTL integrated circuits, are presented. This approach differs from contemporary ideas which depend on the use of digital multipliers in either custom VLSI designs or using standard signal processing chips. It offers high-bandwidth operation at low cost using devices which are already in great demand by the computer market. Alternatively, the algorithm is ideal for implementation as a microprocessor-based system which could operate on real-time voice-bandwidth signals with a minimum of peripheral interface circuitry.