• DocumentCode
    1101121
  • Title

    Worst-Case Analysis of a Resistor Memory Matrix

  • Author

    Lynch, W.T.

  • Author_Institution
    IEEE
  • Issue
    10
  • fYear
    1969
  • Firstpage
    940
  • Lastpage
    942
  • Abstract
    The worst-case output voltage ratio Vs(1)min/Vs(0)maxis derived for a resistor memory matrix having a finite resistance ratio for the bit elements. It is found that the resistance ratio need not be large, and ratios greater than ten are usually sufficient. Input power and output voltage tradeoffs are also discussed.
  • Keywords
    Fixed memories, READ-only memories, resistor matrices, switchable resistor matrices, worst-case analysis of resistor matrices.; Costs; Equivalent circuits; Impedance; Photoconductivity; Resistors; Switches; Telephony; Voltage; Fixed memories, READ-only memories, resistor matrices, switchable resistor matrices, worst-case analysis of resistor matrices.;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/T-C.1969.222549
  • Filename
    1671142
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1101121