Fast-switching analog PLL with finite-impulse response

Author

Levantino, Salvatore ; Milani, Marco ; Samori, Carlo ; Lacaita, Andrea L.

Author_Institution

Dipt. di Elettronica e Informazione, Politecnico di Milano, Milan, Italy

Volume

51

Issue

9

fYear

2004

Firstpage

1697

Lastpage

1701

Abstract

This paper describes a method for speeding up the linear settling response of integer-N phase-locked loops. Extending the discrete-time model of the PLL first proposed by Gardner, simple design rules are derived which guarantee accurate frequency settling in few reference cycles. Simulations show that the proposed design technique improves up to six times the settling time of a conventional design. The stability margins and the noise behavior of the proposed system are analyzed.

Keywords

analogue circuits; circuit noise; circuit stability; phase locked loops; transient response; GPRS; discrete-time model; fast-switching analog PLL; finite-impulse response; frequency synthesizer; integer phase-locked loops; linear settling response; mixed-signal system; noise behavior; noise folding; phase noise; phase-locked loop; stability margins; Bandwidth; Channel spacing; Filters; Frequency; Ground penetrating radar; Phase locked loops; Phase noise; Stability; Switches; Voltage-controlled oscillators; Discrete-time model; GPRS; frequency synthesizer; mixed-signal system; noise folding; phase noise; phase-locked loop; stability;

fLanguage

English

Journal_Title

Circuits and Systems I: Regular Papers, IEEE Transactions on

Publisher

ieee

ISSN

1549-8328

Type

jour

DOI

10.1109/TCSI.2004.834519

Filename

1333219