• DocumentCode
    1101332
  • Title

    Simplified protection system for pad limited CMOS circuits

  • Author

    Orchard-Webb, J.H.

  • Author_Institution
    Mitel Semicond., Kanata, Ont.
  • Volume
    30
  • Issue
    12
  • fYear
    1994
  • fDate
    6/9/1994 12:00:00 AM
  • Firstpage
    948
  • Lastpage
    949
  • Abstract
    Chip sizes for submicrometre technologies are increasingly limited by protection circuitry, wire bonding and testing constraints. The author examines protection circuitry as a chip wide network and optimises it to give enhanced performance for latch-up and ESD without adding to the chip size
  • Keywords
    CMOS integrated circuits; electrostatic discharge; protection; ESD; chip wide network; latch-up; pad limited CMOS circuits; protection circuitry; submicrometre technologies;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19940654
  • Filename
    293060
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1101332