Title :
Simplified protection system for pad limited CMOS circuits
Author :
Orchard-Webb, J.H.
Author_Institution :
Mitel Semicond., Kanata, Ont.
fDate :
6/9/1994 12:00:00 AM
Abstract :
Chip sizes for submicrometre technologies are increasingly limited by protection circuitry, wire bonding and testing constraints. The author examines protection circuitry as a chip wide network and optimises it to give enhanced performance for latch-up and ESD without adding to the chip size
Keywords :
CMOS integrated circuits; electrostatic discharge; protection; ESD; chip wide network; latch-up; pad limited CMOS circuits; protection circuitry; submicrometre technologies;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19940654
