DocumentCode
1101841
Title
Low power dual-port CMOS SRAM macro design
Author
Wang, H. ; Liu, P.C. ; Lau, K.T.
Author_Institution
Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore
Volume
32
Issue
15
fYear
1996
fDate
7/18/1996 12:00:00 AM
Firstpage
1354
Lastpage
1356
Abstract
A novel low power dual-port CMOS SRAM structure is described. The inherent low power advantage is obtained by using current-mode rather than voltage-mode signal transmission. The design of this new dual-port memory cell and current-mode sense amplifier is based on 0.5 μm, 5 V CMOS logic process technology. HSPICE simulations show that the circuits can operate at high speed even if the supply voltage is reduced to 2 V. The dual-port memory cell is most suitable for the design of FIFO buffers
Keywords
CMOS memory circuits; SPICE; SRAM chips; circuit analysis computing; two-port networks; 0.5 micron; 2 to 5 V; FIFO buffers; HSPICE simulations; current-mode sense amplifier; current-mode signal transmission; dual-port CMOS SRAM; low power advantage; macro design; supply voltage;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19960907
Filename
511113
Link To Document