Title :
Noise in digital dynamic CMOS circuits
Author :
Larsson, Patrik ; Svensson, Christer
Author_Institution :
Dept. of Phys. & Meas. Technol., Linkoping Inst. of Technol., Sweden
fDate :
6/1/1994 12:00:00 AM
Abstract :
Dynamic logic is an attractive circuit technique giving reduced area and increased speed for CMOS circuits. Static logic has a major advantage: its superior noise margins. To be able to choose between a static and a dynamic implementation of a design, we need to know the requirements for dynamic logic. Here we try to identify possible errors, estimate the limits and discuss some possible solutions when considering noise in dynamic circuits
Keywords :
CMOS integrated circuits; crosstalk; equivalent circuits; errors; integrated logic circuits; semiconductor device noise; sensitivity analysis; digital dynamic CMOS circuits; dynamic logic; errors; noise margins; CMOS digital integrated circuits; CMOS logic circuits; CMOS process; CMOS technology; Circuit noise; Clocks; Flip-flops; Latches; Logic circuits; Noise generators;
Journal_Title :
Solid-State Circuits, IEEE Journal of
