A static memory cell based on the negative resistance of the gate terminal of p-n-p-n devices

We propose a new static memory cell that is based on bistable operation of a three-terminal p-n-p-n device working in the blocking state. The bistable operation is verified by the measurements of Si/amorphous Si prototypes. The experimental prototypes achieve delay times in the nanosecond range when operating with external gate and anode resistors. In order to decrease the power consumption of the memory cell, we propose to operate it with MOS transistor switches instead of the gate resistors. The memory cell can be integrated into VLSI processes, and is of a size suitable for VLSI applications