A BiCMOS low-power current mode gate

Author

Embabi, S.H.K. ; Brueske, D.E. ; Rachamreddy, K.

Author_Institution

Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA

Volume

29

Issue

6

fYear

1994

fDate

6/1/1994 12:00:00 AM

Firstpage

741

Lastpage

745

Abstract

A controllable BiCMOS low-power current mode logic (LPCML) gate is proposed. The LPCML can be controlled to operate in a high-power mode when its inputs and outputs are in transition. When the gate is idle, it is in a low-power mode and the circuit maintains its output levels with very little tail current. A circuit implementation of the LPCML is also reported with a discussion on its design considerations. A circuit implementation of the LPCML with conventional CML indicates that its delay is greater than that of CML by about 60%. The power consumption of LPCML is proportional to the time it spends in the high-power mode, and, hence, may be significantly lower than that of CML

Keywords

BiCMOS integrated circuits; delays; emitter-coupled logic; equivalent circuits; integrated logic circuits; logic design; logic gates; transient response; BiCMOS IC; CML gate; circuit implementation; current mode logic; delay; high-power mode; low-power current mode gate; power consumption; BiCMOS integrated circuits; CMOS technology; Delay; Energy consumption; Impedance; Logic gates; Switches; Tail; Very large scale integration; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.293123

Filename

293123