DocumentCode :
1102026
Title :
A four-quadrant CMOS analog multiplier for analog neural networks
Author :
Saxena, Navin ; Clark, James J.
Author_Institution :
Div. of Appl. Sci., Harvard Univ., Cambridge, MA, USA
Volume :
29
Issue :
6
fYear :
1994
fDate :
6/1/1994 12:00:00 AM
Firstpage :
746
Lastpage :
749
Abstract :
A four-quadrant CMOS analog multiplier is presented. The multiplier uses the square-law characteristic of an MOS transistor in saturation. Its major advantage over other four-quadrant multipliers is its combination of small area and low power consumption. In addition, unlike almost all other designs of four-quadrant multipliers, this design has single ended inputs so that the inputs do not need to be pre-processed before being fed to the multiplier, thus saving additional area. These properties make the multiplier very suitable for use in the implementation of artificial neural networks. The design was fabricated through MOSIS using the standard 2 μm CMOS process. Experimental results obtained from it are presented
Keywords :
CMOS integrated circuits; analogue processing circuits; linear integrated circuits; multiplying circuits; neural chips; 2 micron; MOSIS; analog neural networks; area; four-quadrant CMOS analog multiplier; power consumption; saturated MOS transistor; single ended inputs; square-law characteristic; Analog computers; Artificial neural networks; CMOS process; Chirp modulation; Concurrent computing; Energy consumption; Frequency modulation; Linearity; MOSFETs; Neural networks;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/4.293124
Filename :
293124
Link To Document :
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