DocumentCode :
1102325
Title :
VLSI for high-performance graphic control utilizing multiprocessor architecture
Author :
Katsura, Koyo ; Maejima, Hideo ; Minorikawa, Kazuo ; Yonezawa, Hiroshi
Author_Institution :
Hitachi-shi Ltd., Ibaraki-ken, Japan
Volume :
32
Issue :
11
fYear :
1985
fDate :
11/1/1985 12:00:00 AM
Firstpage :
2232
Lastpage :
2237
Abstract :
This paper describes the VLSI for high-performance graphic control which utilizes two-level multiprocessor architecture. The VLSI chip is constructed of multiprocessor modules processing in parallel, and each processor module is constructed of multiexecutors using pipeline processing. This dedicated VLSI chip, designated as advanced CRT controller (ACRTC), has three processor modules, each independently controlling drawing, display, and timing. The graphic architecture of the drawing processor, which controls graphic drawing, is described. A high-level graphic language based on an X-Y coordinate system is adopted. High-speed drawing is realized (drawing rate is 500 ns/pixel for drawing a line) by pipeline processing with three executors, the logical address executor, physical address executor, and color data executor.
Keywords :
CMOS technology; Cathode ray tubes; Computer displays; Computer graphics; Control systems; Hardware; Pipeline processing; System performance; Timing; Very large scale integration;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/T-ED.1985.22263
Filename :
1485009
Link To Document :
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