High-power GaAs FET´s prepared by ion implantation

High-power GaAs FET´s have been developed by using ion implantation to form channel layers and n⁺ohmic contact regions. The burn-out characteristics have been improved by introducing n⁺regions with high surface carrier concentration. The source-drain burnout voltage has been found to be more than 40 V. The distributions of saturated source-drain current (Idss) and RF output power of the devices have been found much more uniform than those of power GaAs FET´s prepared by metalorganic chemical vapor deposition (MOCVD). Multichip operation of the FET´s has demonstrated an excellent power combining efficiency due to the good uniformity among the chips. The two-chip device (total gate width WG= 14.4 mm) has delivered 5 W at 10 GHz with 4-dB gain and 23-percent power added efficiency (ηadd). The four-chip device (WG= 28.8 mm) has given 10 W at 8 GHz (gain = 4.5 dB, ηadd= 23 percent). The four-chip device (WG= 48 mm) has developed 15 W at 5 GHz (gain = 8 dB, ηadd= 30 percent).