Title :
Universal NBTI Compact Model for Circuit Aging Simulation under Any Stress Conditions
Author :
Chenyue Ma ; Mattausch, Hans Jurgen ; Matsuzawa, K. ; Yamaguchi, Satarou ; Hoshida, Takeshi ; Imade, M. ; Koh, R. ; Arakawa, Takeshi ; Miura-Mattausch, M.
Author_Institution :
Grad. Sch. of Adv. Sci. of Matter, Hiroshima Univ., Hiroshima, Japan
Abstract :
In this paper, a compact model for the negative bias temperature instability (NBTI) is developed by considering the interface-state generation and the hole-trapping mechanisms. This model shows accurate reproduction of the threshold voltage (Vth) degradations measured from samples fabricated with different dielectric materials as well as processes. A total of eight model parameters are introduced for describing the different degradation origins. The parameter values are verified to exhibit universal properties as a function of the electrical field within the gate oxide (Eox). By implementing the universal NBTI model into the compact model HiSIM, the dynamic NBTI effect and circuit performance degradation can be predicted.
Keywords :
MOSFET; ageing; circuit simulation; dielectric materials; hole traps; interface states; negative bias temperature instability; semiconductor device models; circuit aging simulation; compact model HiSIM; dielectric material; electrical field; gate oxide; hole-trapping mechanism; interface-state generation; negative bias temperature instability; pMOSFET; stress condition; threshold voltage measurement; universal NBTI compact model; Data models; Degradation; Dielectric measurement; Integrated circuit modeling; Interface states; Logic gates; Stress; Negative bias temperature instability (NBTI); hole-trapping; interface-state; modeling; universality;
Journal_Title :
Device and Materials Reliability, IEEE Transactions on
DOI :
10.1109/TDMR.2014.2322673