Scaling the MOS transistor below 0.1 μm: methodology, device structures, and technology requirements

Author

Fiegna, Claudio ; Iwai, Hiroshi ; Wada, Tetsunori ; Saito, Masanobu ; Sangiorgi, Enrico ; Riccò, Bruno

Volume

41

Issue

6

fYear

1994

fDate

6/1/1994 12:00:00 AM

Firstpage

941

Lastpage

951

Abstract

This work is a systematic investigation of the feasibility of MOSFET´s with a gate length below 0.1 μm. Limits imposed on the scalability of oxide thickness and supply voltage require a new scaling methodology which allows these parameters to be maintained constant. The feasibility of achieving sub-0.1 μm MOSFETs in this way is evaluated through simulations of the electrical characteristics of several different device structures and by addressing the most important issues related to the scaling down to ultra-short gate lengths. This study forms a valuable starting point for the understanding of technological requirements for future ULSI

Keywords

MOS integrated circuits; VLSI; hot carriers; insulated gate field effect transistors; integrated circuit technology; semiconductor device models; 0.1 micron; MOS transistor scaling; MOSFET; ULSI; device structures; electrical characteristics; oxide thickness; scalability; scaling methodology; simulations; supply voltage; ultrashort gate lengths; Degradation; Doping; Electric variables; Hot carrier effects; MOSFETs; Research and development; Scalability; Threshold voltage; Tunneling; Ultra large scale integration;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.293306

Filename

293306