• DocumentCode
    1103535
  • Title

    Design of Asynchronous Unit Delays

  • Author

    Batra, Vinod

  • Author_Institution
    IEEE
  • Issue
    10
  • fYear
    1970
  • Firstpage
    896
  • Lastpage
    902
  • Abstract
    An asynchronous unit delay is an n-input n-output asynchronous sequential circuit such that the present value of the output n-tuple is equal to the value of the input n-tuple prior to the last input change. The delay is of significance as a building block for shift register realizations of asynchronous circuits.
  • Keywords
    Asynchronous, equivalent flow table, fundamental mode, pulse controlled.; Asynchronous circuits; Circuit testing; Clocks; Delay; Flip-flops; Pulse circuits; Pulse generation; Sequential circuits; Shift registers; Signal processing; Asynchronous, equivalent flow table, fundamental mode, pulse controlled.;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/T-C.1970.222796
  • Filename
    1671389
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1103535