Abstract :
This paper is an attempt to develop minimization algorithms for switching circuits based on Reed-Muller canonic forms. In particular, algorithms are presented for obtaining minimal modulo 2 or complement modulo 2 sum-of- products (or sums) expressions of any arbitrary single-output or multiple-output switching function with fixed polarities of the input variables.
Keywords :
APL, cellular logic arrays, maximal cliques of a graph, miniimization algorithms, modulo 2 sum-of- products (or sums), Reed-Muller canonic forms.; Circuit synthesis; Codes; Computer languages; Input variables; Iterative algorithms; Large scale integration; Logic arrays; Minimization methods; Programmable logic arrays; Switching circuits; APL, cellular logic arrays, maximal cliques of a graph, miniimization algorithms, modulo 2 sum-of- products (or sums), Reed-Muller canonic forms.;
