Abstract :
A number of schemes for implementing a fast multiplier are presented and compared on the basis of speed, complexity, and cost. A parallel multiplier designed using the carry-save scheme and constructed from 74 series integrated circuits is described. This multiplier multiplies 10-bit by 12-bit binary numbers with a worst- case multiplication time of 520 ns. The cost of the integrated circuits was less than $ 500.
Keywords :
Dadda´s multiplier, digital multipliers, fast multipliers, parallel multipliers, simultaneous multipliers, Wallace´s multipliers.; Costs; Counting circuits; NASA; Dadda´s multiplier, digital multipliers, fast multipliers, parallel multipliers, simultaneous multipliers, Wallace´s multipliers.;
