Title :
A RISC architecture for high-speed data acquisition
Author :
Gribble, Donald L. ; Herzog, James H.
Author_Institution :
Battelle Pacific Northwest Lab., Richland, WA, USA
fDate :
6/1/1994 12:00:00 AM
Abstract :
A RISC architecture specifically designed for selective storage of high-speed digital words is presented. A specialized instruction set is created to allow programmable control of trigger conditions and storage memory. A RISC architecture is required to execute the instruction set and maintain a 10-MHz sample rate. The utility of the RISC system is illustrated by implementing both analog and digital data acquisitions. A prototype system was designed and fabricated for evaluation. Features of this design are presented
Keywords :
computer architecture; data acquisition; reduced instruction set computing; RISC architecture; analog data acquisition; digital data acquisition; high-speed data acquisition; high-speed digital words; programmable control; prototype; selective storage; specialized instruction set; storage memory; trigger conditions; Circuits; Computer architecture; Data acquisition; Information analysis; Logic; Personal digital assistants; Prototypes; Quantization; Reduced instruction set computing; Signal processing;
Journal_Title :
Instrumentation and Measurement, IEEE Transactions on
