An AC-powered experimental memory circuit with a resistively loaded sense circuit

The design and fabrication of an ac-powered experimental memory circuit for Josephson cache memories are reported. The circuit contains a memory cell array and a sense circuit. The sense circuit consists of RCJL gates, symmetrical three-junction sense gates, and transmission lines. An experimental memory circuit has been fabricated by 2-µm Pb-alloy processes. A proper circuit operation, has been verified using a bipolar trapezoidal waveform current. A ±23-percent sense current margin and a ±29-percent OR gate bias current margin were obtained. A typical 130-ps sense time was estimated for a 1-kbit memory by computer simulations.