DocumentCode :
1105222
Title :
Trapezoidal-groove Schottky-gate vertical-channel GaAs FET (GaAs static induction transistor)
Author :
Campbell, P.M. ; Garwacki, W. ; Sears, A.R. ; Menditto, P. ; Baliga, B.J.
Author_Institution :
Naval Research Laboratory, Washington, DC
Volume :
6
Issue :
6
fYear :
1985
fDate :
6/1/1985 12:00:00 AM
Firstpage :
304
Lastpage :
306
Abstract :
This letter reports, the development of a vertical-channel. GaAs FET with the unsaturated 
characteristics of the static induction transistor (SIT) and voltage blocking capability up to 100 V. The device structure utilizes the anisotropic etching properties of GaAs, in which the gate regions are formed by a double-angle evaporation into trapezoidal etched grooves. This single evaporation step simultaneously provides both source and gate metallization, and the novel trapezoidal groove geometry automatically yields a self-aligned gate with separation of source and gate onto different levels, thus eliminating the need for critical alignment arising from source-gate interdigitation.
characteristics of the static induction transistor (SIT) and voltage blocking capability up to 100 V. The device structure utilizes the anisotropic etching properties of GaAs, in which the gate regions are formed by a double-angle evaporation into trapezoidal etched grooves. This single evaporation step simultaneously provides both source and gate metallization, and the novel trapezoidal groove geometry automatically yields a self-aligned gate with separation of source and gate onto different levels, thus eliminating the need for critical alignment arising from source-gate interdigitation.Keywords :
Epitaxial layers; Etching; FETs; Fabrication; Fingers; Gallium arsenide; Implants; Protection; Resists; Substrates;
fLanguage :
English
Journal_Title :
Electron Device Letters, IEEE
Publisher :
ieee
ISSN :
0741-3106
Type :
jour
DOI :
10.1109/EDL.1985.26133
Filename :
1485286
Link To Document :
