An improved circuit model for CMOS latchup

The traditional n-p-n---p-n-p transistor model for CMOS latchup does not adequately describe the latchup path of modern epitaxial devices, a fact which accounts for its inability to produce satisfactory results for devices having a high holding voltage. In this letter a more physically based equivalent circuit representation is discussed. The model better depicts bulk ohmic voltage drops and is more descriptive of the latchup phenomena in epitaxial CMOS devices.