Title :
z-Diagnosis: A Framework for Diagnostic Fault Simulation and Test Generation Utilizing Subsets of Outputs
Author :
Pomeranz, Irith ; Reddy, Sudhakar M. ; Venkataraman, Srikanth
Author_Institution :
Purdue Univ., West Lafayette
Abstract :
Diagnostic fault simulation is used to determine the pairs of faults distinguished by a given test set or test sequence. Diagnostic test generation is used to generate tests that distinguish pairs of faults. Typically, the test sets or test sequences contain tests that detect all the detectable target faults. In this paper, a framework for diagnostic fault simulation and test generation is described, based on structural circuit characteristics called z-sets. These characteristics are used to show that certain fault pairs are guaranteed to be distinguished by a fault detection test set. Such fault pairs do not need to be considered during diagnostic fault simulation or test generation that starts from a fault detection test set. Experimental results for single stuck-at faults in full-scan benchmark circuits demonstrate that only small percentages of fault pairs need to be considered during diagnostic fault simulation or test generation once a fault detection test set is available. The concept of -sets is extended to define z-detections. This concept uses the results of conventional fault simulation to determine additional fault pairs that are guaranteed to be distinguished by a fault detection test set. The concept of z-sets is also extended to define difference-sets (or d-sets) that provide even fewer targets for diagnostic test generation.
Keywords :
circuit simulation; circuit testing; fault simulation; diagnostic fault simulation; diagnostic test generation; difference-sets; fault detection test set; fault pairs; structural circuit characteristics; stuck-at faults; test sequence; z-detection; z-diagnosis; z-sets; Benchmark testing; Character generation; Circuit faults; Circuit simulation; Circuit testing; Electrical fault detection; Fault detection; Fault diagnosis; Life testing; Manufacturing processes; Defect diagnosis; diagnostic fault simulation; diagnostic test generation; scan circuits;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2007.895758