DocumentCode :
1105503
Title :
Self-aligned In0.53Ga0.47As/semi-insulating/n+InP junction field-effect transistors
Author :
Cheng, J. ; Stall, R. ; Forrest, S.R. ; Long, J. ; Cheng, C.L. ; Guth, G. ; Wunder, R. ; Riggs, V.G.
Author_Institution :
AT&T Bell Laboratories, Murray Hill, NJ
Volume :
6
Issue :
7
fYear :
1985
fDate :
7/1/1985 12:00:00 AM
Firstpage :
384
Lastpage :
386
Abstract :
Depletion-mode junction field-effect transistors (JFET´s) with InGaAs p-n junctions grown on compensated Fe:InP or highly resistive In0.52Al0.48As isolation layers grown on n+-InP substrates have been fabricated using a combination of molecular-beam epitaxy and metalorganic chemical vapor deposition growth techniques. Using a self-aligned gate technology with a 1-µm gate length, devices with high transconductance (80 mS/mm), low leakage current (<100 nA), and a gate-to-source capacitance of 0.4 pF have been fabricated. This is apparently the first report where InP-based alloy FET´s have been fabricated on an isolated n+-substrate. This structure has application to monolithically integrated photoreceivers.
Keywords :
Chemical technology; Chemical vapor deposition; FETs; Indium gallium arsenide; Isolation technology; Leakage current; Molecular beam epitaxial growth; P-n junctions; Substrates; Transconductance;
fLanguage :
English
Journal_Title :
Electron Device Letters, IEEE
Publisher :
ieee
ISSN :
0741-3106
Type :
jour
DOI :
10.1109/EDL.1985.26163
Filename :
1485316
Link To Document :
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