Title :
Performance optimization using template mapping for datapath-intensive high-level synthesis
Author :
Corazao, Miguel R. ; Khalaf, Marwan A. ; Guerra, Lisa M. ; Potkonjak, Miodrag ; Rabaey, Jan M.
Author_Institution :
Intel Corp., Santa Clara, CA, USA
fDate :
8/1/1996 12:00:00 AM
Abstract :
This paper introduces a new approach to performance-driven template mapping for high-level synthesis. Template mapping, the process of mapping high-level algorithmic descriptions to specialized hardware libraries or instruction sets, involves template matching, template selection, and clock selection. Efficient algorithms for each are presented, and novel issues such as partial matching are addressed. The paper focuses on datapath-intensive ASIC design, though the concepts are also highly applicable to compiler development. Experimental results on examples from real applications show significant improvements in throughput with limited area overhead
Keywords :
application specific integrated circuits; circuit optimisation; clocks; high level synthesis; instruction sets; integrated circuit design; logic CAD; ASIC design; area overhead; clock selection; compiler development; datapath-intensive high-level synthesis; instruction sets; partial matching; performance optimization; specialized hardware libraries; template mapping; template matching; template selection; Application specific integrated circuits; Clocks; Delay; Hardware; High level synthesis; Integrated circuit synthesis; Libraries; Logic; Optimization; Throughput;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
