Automation of IC layout with analog constraints

Author

Malavasi, Enrico ; Charbon, Edoardo ; Felt, Eric ; Sangiovanni-Vincentelli, Alberto

Author_Institution

Cadence Design Syst. Inc., San Jose, CA, USA

Volume

15

Issue

8

fYear

1996

fDate

8/1/1996 12:00:00 AM

Firstpage

923

Lastpage

942

Abstract

A methodology for the automatic synthesis of full-custom IC layout with analog constraints is presented. The methodology guarantees that all performance constraints are met when feasible, or otherwise, infeasibility is detected as soon as possible, thus providing a robust and efficient design environment. In the proposed approach, performance specifications are translated into lower-level bounds on parasitics or geometric parameters, using sensitivity analysis. Bounds can be used by a set of specialized layout tools performing stack generation, placement, routing, and compaction. For each tool, a detailed description is provided of its functionality, of the way constraints are mapped and enforced, and of its impact on the design flow. Examples drawn from industrial applications are reported to illustrate the effectiveness of the approach

Keywords

analogue integrated circuits; application specific integrated circuits; circuit layout CAD; integrated circuit layout; network routing; sensitivity analysis; IC layout; analog constraints; automatic synthesis; compaction; design environment; design flow; full-custom IC; geometric parameters; lower-level bounds; parasitics; performance constraints; placement; routing; sensitivity analysis; specialized layout tools; stack generation; Analog circuits; Analog integrated circuits; Automation; Integrated circuit interconnections; Integrated circuit layout; Integrated circuit synthesis; Robustness; Routing; Sensitivity analysis; Thermal degradation;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.511572

Filename

511572