DocumentCode
1105725
Title
Automatic layout recycling based on layout description and linear programming
Author
Shigehiro, Yuji ; Nagata, Takashi ; Shirakawa, Isao ; Arungsrisangchai, Itthichai ; Takahashi, Hiromitsu
Author_Institution
Fac. of Eng., Osaka Univ., Japan
Volume
15
Issue
8
fYear
1996
fDate
8/1/1996 12:00:00 AM
Firstpage
959
Lastpage
967
Abstract
When a fabrication process is renewed, of practical importance is how to make the best use of layout resources so far accumulated for old fabrication processes. The present paper describes an automatic recycling system for layout data once used dedicatedly for functional cells of the standard-cell level. The main process of this system is i) to transform given layout data into a layout description format expressed in parameters associated with shapes, sizes, and locations of layout elements, and then ii) to resynthesize an optimal layout in accordance with a new set of design rules by means of a graph theoretic linear programming approach. A part of implementation results is also shown
Keywords
VLSI; circuit layout CAD; circuit optimisation; graph theory; integrated circuit layout; linear programming; VLSI; automatic layout recycling; design rules; fabrication processes; graph theoretic linear programming; layout description; layout description format; layout elements; linear programming; optimal layout resynthesis; Design automation; Fabrication; Layout; Linear programming; Process design; Productivity; Recycling; Shape; Signal design; Systems engineering and theory;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/43.511575
Filename
511575
Link To Document