DocumentCode
1105778
Title
A neural network model for multilayer topological via minimization in a switchbox
Author
Funabiki, Nobuo ; Nishikawa, Seishi
Author_Institution
Dept. of Inf. & Comput. Sci., Osaka Univ., Japan
Volume
15
Issue
8
fYear
1996
fDate
8/1/1996 12:00:00 AM
Firstpage
1012
Lastpage
1020
Abstract
This paper presents a new approach using a neural network model for the multilayer topological via minimization problem in a switchbox. Our algorithm consists of three steps: 1) dividing multiterminal nets into two-terminal nets, 2) finding a layer-assignment of the two-terminal nets by a neural network model so as to minimize the number of unassigned nets, and 3) embedding one via for each unassigned net by Marek-Sadowska´s algorithm. The neural network model is composed of N×M processing elements to assign N two-terminal nets in an M-layer switchbox. The performance of our algorithm is verified by 15 benchmark problems where it can find optimum or near-optimum solutions. In the two-layer Burstein´s switchbox, our algorithm finds a 15-via solution while the best known solution requires 20 vias
Keywords
VLSI; circuit layout CAD; circuit optimisation; integrated circuit layout; minimisation of switching nets; multiterminal networks; network topology; neural nets; layer-assignment; multilayer switchbox; multilayer topological via minimization; multiterminal net division; neural network model; two-layer Burstein switchbox; two-terminal nets; Heuristic algorithms; Intelligent networks; Multi-layer neural network; Neural networks; Pins; Production systems; Routing; Space technology; Very large scale integration; Wires;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/43.511580
Filename
511580
Link To Document