DocumentCode
1106009
Title
A table reduction technique for logarithmically architected digital filters
Author
Frey, M.L. ; Taylor, F.J.
Author_Institution
Massachusetts Institute of Technology, Cambridge, MA
Volume
33
Issue
3
fYear
1985
fDate
6/1/1985 12:00:00 AM
Firstpage
718
Lastpage
719
Abstract
The logarithmic number system (LNS) has been shown to offer high speed and precision metrics. Unfortunately, in practice, its precision is limited by the addressing space of high-speed semiconductor memory. An algorithm is presented which significantly reduces this memory requirement. As a result, both high speeds and precision can be obtained using the existing ECL, HMOS, or bipolar hardware.
Keywords
Arithmetic; Artificial intelligence; Bridges; Data compression; Digital filters; Dynamic range; Encoding; Hardware; Semiconductor memory; Table lookup;
fLanguage
English
Journal_Title
Acoustics, Speech and Signal Processing, IEEE Transactions on
Publisher
ieee
ISSN
0096-3518
Type
jour
DOI
10.1109/TASSP.1985.1164597
Filename
1164597
Link To Document