The Realization of Polylinear Sequential Circuits Using Flip-Flop Memory

In this paper there are developed simple processes for deriving, for finite synchronous sequential machines, polylinear sequential circuit realizations using trigger, set–reset, or J–K flip-flops as the memory elements. It is shown that each such realization is directly obtainable from a graph analogous to the reverse state diagram of the given machine; the latter graph was shown in a former paper by this author to correspond to a polylinear sequential circuit realization using delays for memory. The processes consist of the straightforward steps in the construction of the reverse state diagram analogs. Almost polylinear sequential circuits are defined, and it is shown how certain proper subgraphs of the aforementioned graphs can be used to derive these circuits.