CMOS device isolation using the selective-etch-and-refill-with-EPI (SEREPI) process

A technique has been developed for forming wells in a silicon substrate for CMOS IC´s with an oxide layer providing lateral isolation between adjacent devices. The silicon in the wells is etched; oxide is formed on the sidewalls of the wells; and the wells are refilled with selectively deposited epitaxial silicon. Ring oscillators and submicrometer n- and p-channel MOS transistors have been fabricated using this isolation technique, and special latch-up test structures have been investigated.