Abstract :
Two procedures are presented for generating fault detection test sequences for large sequential circuits. In the adaptive random procedure one can achieve a tradeoff between test generation time, length, and percent of circuit tested. An algorithmic path-sensitizing procedure is also presented. Both procedures employ a three-valued logic system. Some experimental results are given.
Keywords :
Digital logic simulation, fault detection test generation, random test generation, S-algorithm, sequential circuits, three-valued simulation.; Circuit faults; Circuit simulation; Circuit testing; Electrical fault detection; Electrons; Fault detection; Fault diagnosis; Logic testing; Sequential analysis; Sequential circuits; Digital logic simulation, fault detection test generation, random test generation, S-algorithm, sequential circuits, three-valued simulation.;
