DocumentCode
1107120
Title
A Nand Model ror Fault Diagnosis in Combinational Logic Networks
Author
Hayes, John P.
Author_Institution
IEEE
Issue
12
fYear
1971
Firstpage
1496
Lastpage
1506
Abstract
A network model colled the normal NAND model is introduced for the study of fault diagnosis in combinational logic circuits. It is shown that every network can be transformed into an equivalent normal NAND network from which all the information pertaining to the diagnosis of the original network con be obtained. The use of this model greatly simplifies fault analysis and test generation.
Keywords
Combinational networks, fault diagnosis, fault masking, indistinguishable faults, multiple fault detection, NAND networks.; Circuit faults; Circuit testing; Combinational circuits; Digital systems; Fault detection; Fault diagnosis; Integrated circuit modeling; Intelligent networks; Logic; System testing; Combinational networks, fault diagnosis, fault masking, indistinguishable faults, multiple fault detection, NAND networks.;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/T-C.1971.223162
Filename
1671755
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