Title :
A Blind Baud-Rate ADC-Based CDR
Author :
Ting, Chih-Hung ; Liang, Justin ; Sheikholeslami, Ali ; Kibune, Masaya ; Tamura, H.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON, Canada
Abstract :
This paper proposes a 10-Gb/s blind baud-rate ADC-based CDR. The blind baud-rate operation is made possible by using a 2UI integrate-and-dump filter, which creates intentional ISI in adjacent bit periods. The blind samples are interpolated to recover center-of-the-eye samples for a speculative Mueller-Muller PD and a 2-tap DFE operation. A test chip, fabricated in 65-nm CMOS, implements a 10-Gb/s CDR with a measured high-frequency jitter tolerance of 0.19 UIPP and ±300 ppm of frequency offset.
Keywords :
CMOS integrated circuits; analogue-digital conversion; clock and data recovery circuits; 2-tap DFE operation; 2UI integrate-and-dump filter; adjacent bit periods; analog-to-digital converter; blind baud-rate ADC-based CDR; center-of-the-eye samples; clock and data recovery; high-frequency jitter tolerance; intentional ISI; size 65 nm; speculative Mueller-Muller PD; Clocks; Decision feedback equalizers; Feedback loop; Interpolation; Jitter; Receivers; Synchronization; ADC-based clock and data recovery (CDR); Mueller–Muller PD (MMPD); all-digital CDR; baud-rate CDR; blind-sampling CDR;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2013.2279023
