An FPGA-Based Transient Error Simulator for Resilient Circuit and System Design and Evaluation

Error detection and correction (EDAC) has become more important with continued device scaling. We propose a field-programmable gate array (FPGA)-based simulator to accelerate the transient simulation of pipeline-level EDAC circuits and their interactions with circuits under test (CUTs). The simulator incorporates the CUT delay profile, the CUT error profile, and the EDAC model. The FPGA-based simulator captures the fine-grained interactions between the CUT and EDAC for the evaluation of the effectiveness of EDAC and its tuning. The simulator is constructed based on parameterized models, making it general purpose and widely applicable. We demonstrate the capability of this simulator in the evaluation of two popular pipeline-level EDAC designs, i.e., preedge EDAC and postedge EDAC, using synthesized processors that operate under generic error and noise models. The proposed error simulator uncovers key insights to help guide EDAC designs.