A new analytical three-dimensional model for substrate resistance in CMOS latchup structures

A new analytical model based on solving the three-dimensional Laplace equation has been developed to calculate the substrate-spreading resistance of a latchup-sensitive path in internal CMOS structures. This model also provides an analytical closed-form expression for the substrate potential as functions of the structural parameters in the substrate, the dimensions of majority-carrier injector, and the majority-carrier current density across the injector. The calculated results based on the developed model have been compared with existing experimental results, and good agreement has been obtained.