DocumentCode
1107994
Title
A fully operational 1-kbit HEMT static RAM
Author
Kobayashi, Naoki ; Notomi, Seishi ; Suzuki, Masahisa ; Tsuchiya, Takuma ; Nishiuchi, Koich ; Odani, Kouichiro ; Shibatomi, Akihiro ; Mimura, Takashi ; Abe, Masayuki
Author_Institution
Fujitsu Laboratories, Ltd., Atsugi, Japan
Volume
33
Issue
5
fYear
1986
fDate
5/1/1986 12:00:00 AM
Firstpage
548
Lastpage
553
Abstract
In this paper we describe the current status of materials and fabrication technologies, and optimal design of a memory cell, and the performance of fully functional 1-kbit HEMT SRAM´s. The surface defect density on MBE-grown wafers has been reduced to less than 100 cm-2by improving MBE technology. Standard deviations of threshold voltages are 6.7 and 11.8 mV for enhancement-type and depletion-type HEMT´s, respectively, measured in a 10 mm × 10 mm area. These deviations are sufficiently small for DCFL circuits. Memory cell design parameters have been optimized by circuit simulation, where the effects of variations in threshold voltages are taken into account. Full function of 1-kbit SRAM´s has been confirmed by marching tests and partial galloping tests. The RAM chips have also shown excellent uniformity in access time. The difference between maximum and average values on the RAM chip is 4 percent.
Keywords
Area measurement; Circuit simulation; Circuit testing; Design optimization; Fabrication; HEMTs; Measurement standards; Random access memory; Read-write memory; Threshold voltage;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/T-ED.1986.22531
Filename
1485748
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