Asynchronous Unit Delays

This paper considers the problem of designing an n-input, n-output, asynchronous unit delay (AUD) [2], [7], [13]. In the general case, all input changes are allowed in an AUD. However, the restricted case where only single input changes are allowed has been investigated in detail. Starting with linear single error-correcting codes, an unusual method of obtaining a uniquely reduced flow table of a restricted AUD is developed. Such a reduced table has 2k substitution property (SP) partitions [15] on the set of internal states whose product is the zero partition, where k is the smallest integer equal to or greater than log2 n. Hence, the state behavior of an n-input n-output restricted AUD is realizable by 2k two-state sequential circuits connected in parallel [15]. A direct algorithm for obtaining this realization is also given.